A flip chip assembly includes a direct electrical connection of a downward facing (that is, “flipped”) semiconductor chip, or die, onto a carrier, such as a ceramic substrate or a circuit board, using conductive bump bond pads of the chip. Flip chip assemblies are typically made by placing solder bumps on the bump bond pads of the chip, attaching the solder bumped chip to a carrier, and applying an adhesive underfill between the chip and the carrier.
The bumps of the flip chip assembly serve several functions but are susceptible to failures caused by stresses. Of those functions, the bumps provide electrical conductive paths from the chip to the substrate on which the chip is mounted. The bumps also provide part of the mechanical mounting of the chip to the substrate. Unfortunately, bumps are prone to cracking generally caused by stresses, including stress caused by thermal expansion mismatch between the chip and the carrier substrate. The significant difference of coefficients of thermal expansion introduces stress to the structure when thermal changes occur. Most of the stress concentrates on the corners of the chip and/or flip chip assembly, and the larger the chip, the more stress concentration on the die and/or flip chip assembly. FIG. 2 is a portion of a flip chip assembly illustrating a solder ball or bump 40 mounted to a bond pad 30 of a chip 20. Due to stress caused by the thermal expansion mismatch between the materials in the flip chip assembly, a crack 50 develops in solder bump 40. Such cracks may form more easily under the stress experienced at the joint and may easily propagate across the length of the solder bump 40.
The use of copper in the metal bumps further worsens the problem. Since copper is rigid, a high stress may be applied on the solders adjoining the copper bumps and hence the solders are more prone to cracking.
One solution to the problem caused by differences in coefficients of thermal expansion is to fill the gap between the chip and the substrate using an epoxy underfill. Underfill helps spread the stress and protect the solder bumps or balls. But sometimes the underfill has a high coefficient of thermal expansion that creates a mismatch between the expansion of the chip and the underfill. This mismatch introduces more stress in the package that can result in failures.
Wafer level chip scale package (WLCSP) has been introduced in recent years for generally increasing density, performance, and cost-effectiveness, while decreasing the weight and size of the devices in the electronic packaging industry and to fulfill market demands toward increased miniaturization and functionality. One disadvantage of current WLCSP technology is the formation of cracks between the solder ball and the electrode post. The solder ball or bump is typically placed onto the bump electrode or post directly, relying on the soldered joint for structural integrity. The different layers making up the WLCSP device typically have different coefficients of thermal expansion. As a result, a relatively large stress derived from this difference is exhibited on the joint between the post and the bump electrode, which often causes cracks to form in the bonding area between the bump electrode/post and the solder ball or bump.